IEEE

Application of Machine Learning Approaches for Power Estimation of Digital VLSI Circuits at Register Transfer Level

Abstract: In VLSI, estimation of power, performance, and area at appropriate steps during the design process is necessary to meet required specifications. In digital VLSI circuit design, early-stage ...
Semiconductor Engineering

LLM-Powered Automatic VLSI Design Flow Tuning Framework

A new technical paper titled “CROP: Circuit Retrieval and Optimization with Parameter Guidance using LLMs” was published by researchers at Duke University and Synopsys. “Modern very large-scale ...
siliconsemiconductor

The 2025 Symposium on VLSI Technology & Circuits calls for papers

The 2025 Symposium on VLSI Technology & Circuits will deliver a unique convergence of technology and circuits for the microelectronics industry to maximize the synergy across both domains. The 45th ...
IEEE

Dual Multimodal Fusions With Convolution and Transformer Layers for VLSI Congestion Prediction

Abstract: In very large scale integration (VLSI) circuit physical design, precise congestion prediction during placement is crucial for enhancing routability and accelerating design processes.
EDN

Power Tips #136: Design an active clamp circuit for rectifiers at a high switching frequency

In vehicle electrical systems, a high- to low-voltage DC/DC converter is a reversible electronic device that changes the DC from the vehicle’s high-voltage (400 V or 800 V) battery to a lower DC ...
Scientific Research Publishing

K. Roy and S. C. Prasad, “Low-Power CMOS VLSI Circuit Design,” Wiley Interscience Publications, New York, 2000, pp. 28-29.

ABSTRACT: A new circuit technique for 65 nm technology is proposed in this paper for reducing the subthreshold and gate oxide leakage currents in idle and non idle mode of operation for footerless ...