Semiconductor Engineering

Automatic Layout Generator Targeting Region-based Layouts for Advanced FinFET-Based Full-Custom Circuits (UT Austin/NVIDIA)

A technical paper titled “AutoCRAFT: Layout Automation for Custom Circuits in Advanced FinFET Technologies” was published by researchers at UT Austin and NVIDIA. “This paper presents AutoCRAFT, an ...

TSMC's 2nm N2 process officially enters volume production

What just happened? TSMC has begun volume production of chips based on its N2 process technology, marking a major new step in 2nm-class node manufacturing. The company disclosed the milestone on its ...
IEEE

Stress-Related Local Layout Effects in FinFET Technology and Device Design Sensitivity

Abstract: Transistor characteristics in advanced technology nodes are strongly impacted by devices design and process integration choices. Variation in the layout and pattern configuration in close ...
IEEE

Impact of Oxide Diffusion Space Effect on 14-nm FinFET Performance and Layout-Driven Optimization for Advanced Digital Circuits

Abstract: With the continuous scaling down of the feature size, the effect of shallow trench isolation (STI) on integrated circuit (IC) performance has become increasingly critical. This study ...